Course instructor

• CHERIF Bilel

Documentation

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      '    '          '                '       '          '    )/     
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==========================================================================
| --------------------------Choose your weapon---------------------------|
|------------------------------------------------------- Try this at home|
==========================================================================
1. Read TRM (too many pages => Hardcores).
2. Read Zynq book (no technical details => Bored and have nothing to do).
3. Code at home and hack the bsp! ( Requires 1&2 => Brave hearts).
4. Read the chronicles of microzed ( complete simple apps tutos => lazy).

Student@insa:~/be_zynq/course$

• Zynq book link : un livre sur le SOC Zynq de renommée internationale
• Altera (le concurrent de ZYNQ, utilise le même contrôleur d’interruption que ZYNQ puisqu’il est fabriqué par ARM) propose une documentation plus digeste que celle de ARM ou Xilinx. link
• ARM A9 link Intro ARM9 faite par Altera
• Zynq TRM link
• Vivado HLS user manual link

Course files

• Course 0x00 (overview) link

• Course 0x01 link

• Course 0x01 part 2 link

• Course 0x02 link

TP Files

TP 01 doccuments

• TP0x01 link
• TP0x01 guide link
• Trying to explain IRQ handling mechanism in one page link
• Bare metal drivers doccumentation link
• Cortex A9 Processor Exception Handling (ckeck this link for a better understanding of the xilinix supplied exception handler page 23) link

• Zybo referance manual link

• TP0x01 source code link

TP 02 doccuments

• TP0x02 link (a report should be sent to my email by the end of the TP)(this is a two sessions TP)

  1. TB example link

• Constraints file link
• Video tutorials :

Thing	Link
Adding constraints file
IP creator
IP packaging
Writing to memory addresses

TD

Double handshake protocol TD1

• TD0x01 link

  Sorry for the mistake on td 01. Question should be :

  • Extract the condition using the ready and valid signals to allow reading the data line.
  • Write a process that allows to reset the ready signal using rst signal and to set the ready signal.
  • Write the process that allows storing the content of data an internal register of the slave module when the handshake occurs and reset the register content to zeros when a reset occurs.
  • write a testbench to validate your hdl module.

• Testbench example link
• Exo1 source codes :

  1. TB EX01 link

Hardware debug TD2

• TD0x02 link
• ILA documentation link
• JTAG to AXI Master documentation link
• ILA video Tutorial link

Final project

In this project we will develop a prototype pf a guitar multi-effects pedal (we will use just two effects to demonstrate the feasibility of the Project).

• Project doccument link
• Constraints file link
• Zybo audio control IP link
• audio driver source code link
• SSM2603 datasheet link
• VHDL Testbench generation tool here

  
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| .--------------. || .--------------. || .--------------. || .--------------. |
| |  _______     | || |     ____     | || |     ______   | || |  ___  ____   | |
| | |_   __ \    | || |   .'    `.   | || |   .' ___  |  | || | |_  ||_  _|  | |
| |   | |__) |   | || |  /  .--.  \  | || |  / .'   \_|  | || |   | |_/ /    | |
| |   |  __ /    | || |  | |    | |  | || |  | |         | || |   |  __'.    | |
| |  _| |  \ \_  | || |  \  `--'  /  | || |  \ `.___.'\  | || |  _| |  \ \_  | |
| | |____| |___| | || |   `.____.'   | || |   `._____.'  | || | |____||____| | |
| |              | || |              | || |              | || |              | |
| '--------------' || '--------------' || '--------------' || '--------------' |
 '----------------'  '----------------'  '----------------'  '----------------' 
     
===============================================================================
| ----------------------------------Ba byee-----------------------------------|
|---------------------------------------------------------------- Good luck!!!|
===============================================================================

Student@insa:~/be_zynq/course$ ./be_zynq
Student@insa:~/be_zynq/course$ Press any key to rock and roll: